library verilog;
use verilog.vl_types.all;
entity uart_tx is
    generic(
        BPS             : integer := 5208
    );
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        din             : in     vl_logic_vector(7 downto 0);
        din_vld         : in     vl_logic;
        rdy             : out    vl_logic;
        dout            : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of BPS : constant is 1;
end uart_tx;
